This invention relates to a thin film transistor. In particular, this invention is suitable for use in a thin film transistor for an image display device driver and peripheral circuits thereof. This invention is effective particularly to the structure of a polycrystal silicon thin film transistor manufactured at a low temperature process but it is not restricted only thereto and is applicable, for example, also to a device so-called high temperature polysilicon thin film transistor.
The structure of an existent thin film transistor (hereinafter simply referred to as TFT) for use in a liquid crystal display (hereinafter referred to as LCD) is described in, for example, Japanese Patent No. 2948965. This is an example of a thin film transistor in which a lightly doped domain (hereinafter simply referred to as LDD) is formed to a source-drain region (hereinafter simply referred to as LDD TFT). At present, such a structure is general for use in display. Further, as described in, for example, Japanese Patent Laid-open Hei 7-202210, a TFT of a structure in which a gate electrode is overlapped to the LDD portion (Gate Overlapped LDD (hereinafter simply referred to as GOLD)) is also used. As a method of manufacturing LDD TFT, the following manufacturing method has been known. When a gate electrode is processed using a resist mask, the gate electrode is etched laterally (side etching), and then a resist is baked. Thereafter, impurity is doped to the source-drain using the resist as a mask and doping is conducted to the LDD portion after removal of the resist.
Further, it is a general method of conducting doping to LDD after processing the gate electrode, then forming an insulation film layer (side wall) only on the side wall of the gate electrode and conducting doping to the source-drain region in this state. Such a method is described in, for example, Japanese Patent Laid-open Hei 11-160736.
On the other hand, in GOLD TFT, a step of conducting the doping to the LDD portion simultaneously by ion implantation to the source-drain after processing the gate electrode in a convex shape is also adopted. This is described in, for example, Japanese Patent Laid-open Hei 7-202210.
An object of this invention is to provide a low temperature polysilicon TFT capable of ensuring a high reliability over a long period of time. Another object of this invention is to consistently provide a low temperature polysilicon TFT capable of ensuring high reliability for such a long period of time. Thus, LCD of high reliability can be supplied consistently.
The prior arts described above involve the following drawbacks. A first problem in the prior art is that damages increase upon doping to a gate oxide film/semiconductor interface when doping is applied to the LDD portion. This is attributable to a failure to consider the dopant profile in the direction of the depth in a semiconductor thin film in this case. For example, assume a case in which the gate insulation film comprises SiO2 and the semiconductor thin film comprises Si. In a case where doping is applied by ion implantation or ion doping to the Si thin film, when doping is applied such that the concentration peak of the dopant is at the center of the semiconductor thin film, the amount of damage upon doping has a peak in SiO2 at a shallower region, or near the SiO2/Si interface. Usually, doping is conducted under such a condition. This is because such damage exhibits a peak at the depth 70 to 80% of the depth of the concentration peak in ion implantation with about 100 keV. This is reported in, for example, Journal of Applied Physics (D. K. Brice: J. Appl. Phys.), Vol 46, p 3385 (1975).
Similar damages may also be considered in the ion doping. In the TFT manufacturing process using polysilicon formed at low temperatures, the maximum heat treatment temperature is about 600xc2x0 C. at the highest. The damage in SiO2 or at the SiO2/Si interface caused by doping is not recovered completely at this temperature. Usually, the damage is terminated by termination with nitrogen from an SiN film in the passivation step and electrically inactivated.
However, since the terminated defects are again activated electrically by hot carriers generated during operation of TFT, the oxide film and the interface containing much ion implantation damage tends to be degraded during use of TFT. Accordingly, this causes shortening of the LCD life. Therefore, it is difficult to consistently obtain an LCD of high reliability using a low temperature polysilicon TFT by the existent LDD manufacturing method.
On the other hand, in the method in which the gate electrode is formed in a convex shape and doping to the source-drain and LDD is collectively conducted, there has arisen a problem that the LDD concentration tends to be varied. For the film thickness in the thin portion of the gate electrode, variation by about several percent is inevitably formed in a substrate due to variation in a dry etching process or the like. In this case, concentration in the LDD portion varies by about 10%. This is due to the fact that the dopant concentration in the source-drain region is 1xc3x971020/cm3 or more, whereas the dopant concentration in the LDD portion is about 1xc3x971017/cm3xe2x88x921xc3x971020/cm3 and dopings different in the concentration by two orders of magnitude or more are conducted collectively.
The basic concept of this invention can be expressed as below.
A first typical aspect of this invention is a thin film transistor mounted on an insulator substrate, the thin film transistor comprising a semiconductor thin film, a gate insulation film formed in contact with the semiconductor thin film and a gate electrode, in which the semiconductor thin film has a first impurity region and a second impurity region opposed to each other, and has a third impurity region disposed adjacent to at least one of the first impurity region or the second impurity region, the impurity concentration in the third impurity region is lower than the impurity concentration of the first impurity region or the second impurity region, and the concentration distribution in the third impurity region in the direction crossing the insulator substrate is minimum or maximum near an interface between the gate insulation film and the semiconductor thin film in the semiconductor thin film.
A second aspect of this invention is a thin film transistor mounted on an insulator substrate, the thin film transistor comprising a semiconductor thin film formed adjacent to the insulator substrate, a gate insulation film and a gate electrode, in which the semiconductor thin film has a first impurity region and a second impurity region opposed to each other and a third impurity region disposed adjacent to at least one of the first impurity region or the second impurity region, the impurity concentration of the third impurity region is an impurity concentration lower than the impurity concentration of the first impurity region or the second impurity region, and the distribution of the concentration of the impurity concentration in the third impurity region in the direction crossing the insulator substrate is minimum or maximum near an interface between the gate insulation film and the semiconductor thin film in the semiconductor thin film.
It is often preferable that a minimum or maximum level for the distribution of the impurity concentration in the third impurity region is present within a range of about ⅕ of the thickness of the semiconductor thin film with respect to an interface between the gate insulation film and the semiconductor thin film or an interface between the insulator substrate and the semiconductor thin film.
Further, another aspect in which at least one insulation layer or a desired member is disposed between the insulator substrate and the thin film transistor may also be considered. That is, the thin film transistor may be formed regarding a member formed with at least one insulation layer or the desired member as an insulator substrate. The aspect in which at least one insulation layer is disposed between the insulator substrate and the thin film transistor is useful for favorably forming a semiconductor thin film to be mounted on the insulation substrate. Further, doping to the third impurity region is preferably conducted separately from the doping to the first and second impurity regions.
Damage caused by the doping in the LDD portion can be decreased by conducting doping while changing the position for the concentration peak of the concentration profile in the direction of the depth during doping from the existent center for the semiconductor thin film toward the gate insulation film/semiconductor thin film interface or toward the semiconductor thin film/insulator substrate interface in the semiconductor thin film. In this case, when an insulation film is formed on the insulator substrate, the position is changed toward the interface between the semiconductor thin film and the insulation film. The peak position of the dopant, in the laminate is not restricted to in the semiconductor thin film but may be in the gate insulation film, in the insulator substrate or in the insulation film formed on the insulator substrate, and a similar effect can be obtained when it is present also at the interface between the semiconductor thin film and them. It should be noted that the wording of xe2x80x9cgate insulation film/semiconductor thin filmxe2x80x9d or the like shows that the gate insulation film and the semiconductor thin film are formed adjacent to each other, that is, they are laminated for example.